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www.fairchildsemi.com ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/8/11 AN-9736 design guideline of ac-dc converter using fl6961 & fl6300a for 70w led lighting summary this application note describes a design strategy for a power factor correction (pfc) circuit and higher-power conversion efficiency using fl6961 and fl6300a. based on this design guideline and several functions of each controller for led lighting applications, a design example with detailed parameters demonstrates the performance. introduction figure 1 shows the typical application circuit, with the bcm pfc converter in the front en d and the quasi-resonant (qr) flyback converter in the back end. fl6961 and fl6300a achieve high efficiency with relatively low cost for 75~200w applications where bcm and qr operation with a single switch shows best performance. bcm boost pfc converter can achieve better effi ciency with lower cost than continuous conduction mode (ccm) boost pfc converter. these benefits result from the elimination of the reverse- recovery losses of the boost diode and zero-voltage switching (zvs) or near-zvs (also called valley switching) of boost switch. the qr flyback converter for the dc-dc conversion achieves higher effi ciency than the conventional hard-switching converter with valley switching. the fl6961 provides a contro lled on-time to regulate the output dc voltage and achieves natural power factor correction. the maximum on-time of the switch is programmable to ensure safe operation during ac brownouts. the fl6300a ensures thepower system operates in quasi-resonant operation in wide range line voltage and reduces switching loss to minimize switching voltage in drain of the power mosfet. to minimize standby power consumption and improve light-load efficiency, a proprietary green-mode provides off-time modulation to decrease switching frequency and perform extended valley voltage switching to keep to a minimum switching voltage. figure 1. typical application circuit
AN-9736 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/8/11 2 1. basin operation of bcm boost pfc converter the typical boost converter and its operational waveforms are shown in figure 2, figure 3, and figure 4. () g vt ? ? () l vt ?? d co r o o v ? ? () l it q b l figure 2. boost converte r () g vt ? ? () l vt ?? () l it q b l () g vt ? ? () l vt ?? co r o o v ? ? () l it b l (a) switch q is on (b) switch q is off figure 3. switching sequences of the boost converter () og b vvt l ? () l vt on t off t q () l it () g b vt l () g vt g () o vvt ? , (t) lavg i figure 4. one-cycle waveform of the boost converte r 1.1. operation principle when q turns on, the rectifier diode d is reverse-biased and output capacitor c o supplies load current. the rectified ac line input voltage v g (t) is applied to the inductor l b so that inductor current i l ramps up linearly and can be expressed as: i l t v t l (1) when q turns off, the voltage v o -v g (t) is applied to inductor l b and the polarity on the inductor lb is reversed. the diode d is forward-biased in this stage. the energy stored in the inductor l b is delivered to supply load current and output capacitor c o . the inductor current i l can be expressed as: i l t v v t l (2) the on-time of the power mosfet q is determined by the output of the error amplifier that monitors the pre-regulator output voltage. with a low-bandwidth error amplifier, the feedback signal is almost cons tant during a half ac cycle, resulting a fixed on-time of the power mosfet at a specific ac voltage and some certain output power level. therefore, the peak inductor current i lpk automatically follows the input voltage v g(t), achieving a natural power factor correction mechanism. figure 5 shows the typical inductor current waveform during a half ac cycle. figure 5. controlled on-time inducto r current waveform referring to figure 4, considering one switching period the average inductor current, i l,ave (t) can be calculated by the average area of triangle wave form of inductor current: i l, t v t v t v v t t t 2l t (3)
AN-9736 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/8/11 3 2. operation principle of quasi- resonant flyback converter qr flyback converter topology can be derived from a conventional square wave, pulse-width modulated (pwm), flyback converter without additional components. figure 6 and figure 7 show the simplifi ed circuit diagram of a quasi- resonant flyback converter and its typical waveforms. figure 6. schematic of qr flyback converter 2.1. operation principle ? during the mosfet on time (t on ), input voltage (v in ) is applied across the primary-side inductor (l m ). mosfet current (i ds ) increases linearly from zero to the peak value (i pk ). during this time, the energy is drawn from the input and stored in the inductor. ? when the mosfet is turned off, the energy stored in the inductor forces the rectifier diode (d) to turn on. during the diode on time (t d ), the output voltage (vo) is applied across the secondary-side inductor and the diode current (i d ) decreases linearly from the peak value to zero. at the end of t d , all the energy stored in the inductor has been delivered to the output. during this period, the output voltage is reflected to the primary side as v o ? n p /n s . then, the sum of input voltage (v in ) and the reflected output voltage (vo ? n p /n s ) is imposed across the mosfet. ? when the diode current r eaches zero, the drain-to- source voltage (v ds ) begins to oscillate by the resonance between the primary-side inductor (l m ) and the mosfet output capacitor (c oss ) with an amplitude of v o ? n p /n s on the offset of v in , as depicted in figure 7. quasi-resonant switching is achieved by turning on the mosfet when v ds reaches its minimum valu e. this reduces the mosfet turn-on switching loss caused by the capacitance loading between the drain and source of the mosfet. figure 7. typical waveforms of qr flyback converter 3. design considerations this design procedure uses the schematic in figure 1 as a reference. a 70w pfc application with universal input range is selected as a design example. the design specifications are: ? line voltage range: 90~277v ac (60hz) ? output of dc-dc converter: 24v/2.9a (70w) ? pfc output voltage for line voltage: 420v ? minimum pfc switching frequency: > 58khz ? minimum qr flyback switching frequency: > 50khz ? overall efficiency: 90% (pfc: 95%, qr: 95%) 3.1. pfc section 3.1.1. boost inductor design the boost inductor value is determined by the output power and the minimum switching frequency. the voltage-second balance equation for the inductor is: v in t t on v o.pfc v in t t off (4) f s w ,min 1 t o n t o ff 1 t o n v o.pfc 2 v line v o .pf c (5) where v in (t) is the rectified line voltage. v line is rms line voltage; t on is the mosfet conduction time; and v o.pfc is the pfc output voltage.
AN-9736 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/8/11 4 the mosfet conduction time with a given line voltage at a nominal output power is given as: t on 2p out l ?v line (6) where: ? is the overall efficiency; l is the boost inductance; and p out is the nominal output power. using equation 5, the minimum switching frequency of equation 6 can be expressed as: f s w . min ?v line 2p out l v o.pfc 2 v line v o.pfc (7) as shown in figure 5, considering one ac line voltage cycle, the minimum switching fre quency occurs at peak of the ac line voltage. also, the minimum switching frequency may occur in ac maximum or minimum input voltage, depending on the output voltage. therefore, calculate both the maximum and the minimum input voltage and choose the lower inductan ce value. once the output voltage and minimum switching frequency are set, the inductor value is given as: l ?v line max 2p ou t f sw . min v o.pfc 2 v line max v o .pf c (8) where v line,max is the maximum line voltage. as the minimum frequency decreases, the switching loss is reduced, while the inductor size and line filter size increase. thus, the minimum switching frequency should be determined by the trade-off be tween efficiency and the size of magnetic components. the minimum switching frequency must be above 20khz to prevent audible noise. once the inductance value is decided, the maximum peak inductor current at the nomina l output power is obtained at low-line condition as: i l.pk 2 2 p out ?v line.min (9) where v line,min is the minimum line voltage. since the maximum on time is internally limited at 25s, it should be smaller than 25s, as calculated by: t on max 2p out l v line min 20s (10) the number of turns of the boost inductor should be determined considering the core saturation. the minimum number is given as: n boost i l.pk l a b (11) where is ae is the cross-sectional area of core and ? b is the maximum flux swing of the core in tesla. ? b should be set below the saturation flux density. (design example) since the output voltage is 420v for line voltage, the minimum frequency occurs at high-line (277v ac ) and full-load condition. assuming the overall efficiency is 90% and selecting the minimum frequency as 58khz, the inductor va lue is obtained as: l ?v line max 2p out f sw. min v o.pfc 2 v line max v o.pfc 0.9 277 2 70 58 10 420 2 277 420 570h the maximum peak inductor cu rrent at nominal output power is calculated as: i l.pk 2 2 p out ?v line.min 2 2 70 0.9 90 2.44 a t on max 2p out l ?v line min 2 70 570 10 0.9 90 10.9s 20s assuming rm10 core (pc40, a e =85mm 2 ) is used and setting ? b as 0.25t, the primary winding should be: n boost i l.pk l a b 2.44 570 10 85 10 0.25 65.8 turns thus, the number of turns (n boost ) of boost inductor is determined as 65. 3.1.2. auxiliary winding design figure 9 shows the internal block for zero-current detection (zcd) for the pfc. fl6961 indirectly detects the inductor zero-current instant using an auxiliary winding of the boost inductor. the auxiliary winding should be designed such that the voltage of the zcd pin rises above 2.1v when the boost switch is turned off to trigger internal comparator as: n zcd n boost v o.pfc 2 v line.max 2.1v (12) the zcd pin has upper voltage clamping and lower voltage clamping at 10v and 0.3v, re spectively. when the zcd pin voltage is clamped at 0.3v, the maximum sourcing current is 1.5ma and, therefore, the resistor r zcd should be properly designed to limit the current of the zcd pin below 1.5ma in the worst case as: r zcd v in 1.5ma n aux n boost 2 v line.max 1.5ma n aux n boost (13)
AN-9736 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/8/11 5 figure 8. internal block for zcd zcd i n boost n v n . () zcd o pfc in boost n vv n ? figure 9. zcd waveforms (design example) the number of turns for the auxiliary zcd winding is obtained as: n zcd 2.1n boost v o.pfc 2 v line.max 4.83 turn with a margin, n aux is determined as 6 turns. r zcd is selected from: r zcd 2 v line.max 1.5ma n aux n boost 2 277 1.5 10 6 65 24k? as 30 k ? . 3.1.3. current-sensing resistor for pfc fl6961 has pulse-by-pulse current limit function. it is typical to set the pulse-by-current limit level at 20~30 % higher than the maximum inductor current: r cs 0.82 i l.pk 1 k margin (14) where k margin is the margin factor and 0.85v is the pulse-by-pulse current limit threshold. (design example) choosing the margin factor as 35 % , the sensing resistor is selected as: r cs 0.85 i l.pk 1 k margin 0.82 2.441 0.35 0.25? 3.1.4. output capacitor selection for a given minimum pfc output voltage during the hold- up time, the pfc output capacitor is obtained as: c o.pfc 2p out t hold v o.pfc v o.pfc.hld (15) where: p out is total nominal output power; t hold is the required holdup time; and v o.pfc,hld is the allowable minimum output voltage during the hold-up time. for pfc output capacitor, it is typical to use 0.5~1f per 1w output power for 420v pfc output. meanwhile, it is reasonable to use about 1f per 1w output power for variable output pfc due to the larger voltage drop during the hold-up time than 420v output. 3.1.5. design compensation network the feedback loop bandwidth must be lower than 20hz for the pfc application. if the bandwidth is higher than 20hz, the control loop may try to reduce the 120hz ripple of the output voltage and the line current is distorted, decreasing power factor. a capacitor is connected between comp and gnd to attenuate the line freque ncy ripple voltage by 40db. if a capacitor is connected betw een the output of the error amplifier and the gnd, the error amplifier works as an integrator and the error am plifier compensation capacitor can be calculated by: c comp 100 g m 2 2 f line 25 v o.pfc (16) c o.pfc 2p out t hold v o.pfc v o.pfc.hld 2 80 20 10 420 350 60f (design example) assuming the minimum allowable pfc output voltage during the hold-up time is 160v, the capacitor should be: a 68 ? f capacitor is selected fo r the output capacitor.
AN-9736 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/8/11 6 to improve the power factor, c comp must be higher than the calculated value. however, if the value is too high, the output voltage control loop may become slow. 3.2. dc-dc section 3.2.1. determine the reflected output voltage ( v ro ) figure 10 shows the typical operation waveforms of a quasi- resonant flyback converter. when the mosfet is turned off, the input voltage (pfc output voltage), together with the output voltage reflected to the primary (v ro ), is imposed on the mosfet. when the mosfet is turned on, the sum of input voltage reflected to the secondary side and the output voltage is applied across the diode. thus, the maximum nominal voltage across the mosfet (v ds.nom ) and diode are given as: v ds v o.pfc n v o v f v o.pfc v ro (17) where: n v ro v o v f (18) v d v o v o.pfc n v o v o.pfc v ro v o v f (19) by increasing v ro (i.e. the turns ratio, n ), the capacitive switching loss and conduction loss of the mosfet are reduced. this also reduces the voltage stress of the secondary-side rectifier diode. however, this increases the voltage stress on the mosfet. therefore, v ro should be determined by a trade-off between the voltage stresses of the mosfet and diode. it is typical to set v ro such that v ds.nom and v d.nom are 75~85% of their voltage ratings. figure 10. typical waveforms of qr flyback converter (design example) assuming 650v mosfet and 150v diode are used for primary side and secondary side, respectively, with 18% voltage margin: 0.82 650v v ds v o.pfc v ro v ro 0.82 650 v o.pfc 133v 0.82 150 v ds v o v o.pfc v ro v o v f v ro v ds v o.pfc 0.82 150 v o v o v f 106v v ro is determined as 130v. 3.2.2. transformer design figure 11 shows the typical switching timing of a quasi- resonant converter. the sum of mosfet conduction time (t on ), diode conduction time (t d ), and drain voltage falling time (t f ) is the switching period (t s ). to determine the primary-side inductance (l m ), the following parameters should be determined first. minimum switching frequency (f s.qrmin ) the minimum switching frequency occurs at the minimum input voltage and full-load condition, which should be higher than 20khz to avoid audible noise. by increasing f s . qrmin , the transformer size can be reduced. however, this results in increased switc hing losses. determine f s.qrmin by a trade-off between switching losses and transformer size. typically f s.qrmin is set to around 50khz. c comp 100 g m 2 2f line 2.5 v o.pfc 100 125 10 2260 2.5 420 100nf. (design example) 470nf is selected for better power factor.
AN-9736 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/8/11 7 falling time of the mosfet drain voltage (t f ) as shown in figure 11, the mosfet drain voltage fall time is half of the resonant period of the mosfet?s effective output capacitance and primary-si de inductance. the typical value for t f is 0.6~1.2s. non-conduction time of the mosfet (t off ) fl6300a has a minimum non-conduction time of mosfet (8s), during which turning on the mosfet is prohibited. to maximize the efficiency, it is necessary to turn on the mosfet at the first valley of mosfet drain-to-source voltage at heavy-load condition. therefore, the mosfet non-conduction time at heavy load condition should be larger than 8s. although qr flyback is operated in pfc end for normal operation; when d max is calculated to meet all input conditions, it should take in to account the minimum input voltage of v line due to the start sequence between pfc and qr flyback at startup. after determining f s.qr min and t f , the maximum duty cycle is calculated as: d v ro v line v r o 1 f s.qr t f (20) the primary-side induct ance is obtained as: l qr v line d 2 f s.qr p out (21) once l m is determined, the maximum peak current and rms current of the mosfet in normal operation are obtained as: i ds pk v line d l f s.qr (22) i ds rms i ds pk d 3 (23) the mosfet non-conduction time at heavy load is obtained as: t off 1 d f s.qr (24) to guarantee the first valle y switching at heavy-load condition, t off should be larger than 8 s . figure 11. switching timing of qr flyback converter when designing the transformer, the maximum flux density (b) swing in normal operation as well as the maximum flux density (bmax) in transient should be considered. the maximum flux density swing in normal operation is related to the hysteresis loss in the core, while the maximum flux density in transient is related to the core saturation. the minimum number of turns for the transformer primary side to avoid over temperature in the core is given by: n p l i ds pk a b (25) where b is the maximum flux density swing in tesla. if there is no reference data, use b =0.25~0.30t. once the minimum number of turns for the primary side is determined, calculate th e proper integer for n s so that the resulting n p is larger than n p min as: n p nn s n p (26) the number of turns of the auxiliary winding for v dd is given as: n aux v dd v fa v o v f n s (27) where v dd nom is the nominal v dd voltage, typically 18v, and v fa is forward-voltage drop of v dd diode. once the number of turns of the primary winding is determined, the maximum flux density when the drain current reaches its pulse-by-pul se current limit level should be checked to guarantee the transformer is not saturated during transient or fault condition. the maximum flux density (b max ) when drain current reaches i ds pk is given as: b l i ds pk a n p b (28) b max should be smaller than the saturation flux density. if there is no reference data, use b sat =0.35~0.40t.
AN-9736 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/8/11 8 (design example) setting the minimum frequency is 50khz and the falling time is 0.8s: d v ro v line v ro 1 f s.qr t f 130 127 130 15010 0.810 0.48 l qr v line d 2f s.qr p out 0.95 127 0.48 25010 70 500f i ds pk 127 0.48 500 10 5010 2.52a t off 1 d f s.qr 10.48 50 10 10s assuming eer3124 (ae=102mm2) core is used and the flux swing is 0.29t n p l i ds pk a b 500 10 2.52 102 10 0.29 41.8 n p nn s 5.3842.4n p n aux v dd v fa v o v f n s 18 1.2 24.5 86.3 assuming the pulse-by-pulse current limit for pfc output voltage is 120% of peak dr ain current at heavy load: b l i ds pk a n p 500 2.52 1.2 102 42 0.34t 3.2.3. design the valley detection circuit figure 12 shows the det pin circuitry. the det pin is connected to an auxiliary winding by r det and r a . the voltage divider is used for the following purposes: ? detect the valley voltage of the switching waveform for valley voltage switching. this ensures qr operation, minimizes switching losses, and reduces emi. ? produce an offset to compensate the threshold voltage of the peak current limit to provide a constant power limit. the offset is generated in accordance with the input voltage with the pwm signal enabled. ? a voltage comparator and a 2.5v reference voltage provide output ovp. the ratio of the divider determines the output voltage level to stop the gate. figure 12. detection pin section first, determine the ratio of the voltage divider resisters. the ratio of the divider determines what output voltage level to stop gate. in figure 13, the sampling voltage v s is: v s n a n s v o r a r det r a 2.5v (29) where n a is the number of turns for the auxiliary winding and n s is the number of turns for the secondary winding. figure 14 shows the internal valley detection block and the output voltage ovp detection block of fl6300a using auxiliary winding to detect v o . the internal timer (minimum t off time) prevents the system frequency from being too high. first valley switching is activated after minimum t off time of 8 s. the nominal voltage of v s is designed around 80% of the reference voltage 2.5v; thus, the recommended value for v s is 1.9v~2.1v. the output over-voltage protection works by the sampling voltage after th e switching-off sequence. a 4 s blanking time ignores the leakage inductance ringing. if the det pin ovp is triggered, the power system enters latch mode until ac power is removed. figure 13. v oltage sampled after 4s blanking time after switch-off sequence
AN-9736 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/8/11 9 figure 14. output voltage detection block once the secondary-side switching current discharges to zero, a valley signal is generated on the det pin. it detects the valley voltage of the switching waveform to achieve the valley voltage switching. when the voltage of auxiliary winding v aux is negative (as defined in figure 12), the det pin voltage is clamped to 0.3v. r det is recommended as 150k ? to 220k ? to achieve valley voltage switching. after the platform voltage v s in figure 13 is determined, r a can be calculated by equation 14. (design example) setting r det is 200k and v s is around 80% of the reference voltage 2.5v: v s n a n s v o r a r det r a 2.1v r a 2.1 r det n a n s v o 2.1 26.4k ? 3.2.4. current-sensing resistor for pfc fl6300a has pulse-by-pulse current limit function. it is typical to set the pulse-by-current limit level at 20~30 % higher than the maximum inductor current: r cs 0.8 i ds pk 1 k margin (30) where k margin is the margin factor and 0.8v is the cycle- by-cycle current limit threshold. (design example) choosing the margin factor as 35%, the sensing resistor is selected as: r cs 0.8 i ds pk 1 k margin 0.8 2.521 0.35 0.23? 3.2.5. design the feedback circuit figure 15 is a typical feedback circuit mainly consisting of a op-amp and a photo-coupler. r h and r l form a voltage divider for output voltage regulation. r f and c f are adjusted for control-loop compensation. a small-value rc filter (e.g. r fb = 100, c fb = 1nf) placed from the fb pin to gnd can increase stability substantially. the maximum source current of the fb pin is abou t 1.2ma. the phototransistor must be capable of sinking this current to pull the fb level down at no load. the value of the biasing resistor, r bias , is determined as: v op v opd r bias ctr 1.2 10 (31) where v opd is the drop voltage of photodiode, about 1.2v; v op is the output voltage of operational amplifier (assuming about 2.5v); and ct r is the current transfer rate of the opto-coupler. figure 15. feedback circuit the constant voltage and current output is adapted by measuring the actual output voltage and current with some external passive components and op-amp in the reference board. because the output load , the high bright led (hb led), and some passive components effect the ambient temperature, use the feedback path for stable operation.
AN-9736 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/8/11 10 do cc control part cv control part v ref v sen_cv vo v ocv v ref v occ r 5 r 8 r 4 c 1 r 7 c 2 r 1 r 2 r 3 r 6 v sen_cc c 1 c 2 figure 16. feedback circuit for cc/cv operation v ocv v _ cv r r v _ cv v 1 c 1 r v _ cv v d t (32) where the v sen_cv means the sensing output voltage from the output stage and is divided by r 4 and r 8 resistor. sensing resistor r 4 and its value directly effect the cc control block output. normally, the cc block is more dominate than the cv block in steady state and the cv block acts as the over- voltage protection (ovp) at transient or abnormal mode, such as no load condition. the output signal of cc block is determined as: v occ r v _ cc r v r 1 c v _ cc r v r dt (33)
AN-9736 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/8/11 11 3.3. schematic of the evaluation board figure 17. evaluation board schematic r131 433/3216 d205 ll4148 l201 10uh c210 105/2012 c206 33uf/50v q201 mmbt2222a zd201 15b c207 104/2012 r205 392/2012 r202 152/2012 c202 1000uf/35v r118 100/3216 c203 1000uf/35v r122 0r2 2w q102 fqpf8n80 c112 200/2012 r119 4r7/3216 d105 ll4148 r120 151/3216 r130 103/3216 c110 47uf/450v r124 203/3216 r123 224/3216 r117 150k/2w d108 rs1m c117 200/2012 r111 0r2 2w c204 1000uf/35v c205 1000uf/35v r105 433/3216 r106 433/3216 r107 433/3216 r213 153/3216 r129 103/3216 c103 472(y ) c104 472(y ) u201 ka431s 2 3 1 r214 153/3216 r101 473/3216 t2 eer3124 (v10p) 4 3 1 5 6 9 10 7 r102 473/3216 r103 473/3216 r207 473/2012 c101 684/275v c106 33uf/50v c201 1000uf/35v c107 104/2012 d103 egp30j f101 220v/2a d101 kbl06 d203 ll4148 c211 222(y ) r128 473/3216 u102 fl6300 vdd 6 det 1 fb 2 cs 3 hv 8 gate 5 gnd 4 nc 7 l101 ei2820 (v10p) 6 10 1 5 d104 rs1m r212 392/2012 r210 183/2012 r204 753/2012 r208 302/2012 n l c102 334/275v c111 222 1kv r116 150k/2w r203 513/2012 r104 473/3216 r112 394/3216 r113 394/3216 r114 394/3216 r115 682/3216 u202 lm2904 in2(-) 6 in(+) 3 gnd 4 in2(+) 5 in(-) 2 out1 1 vcc 8 out2 7 u101 fl6961 comp 2 inv 1 mot 3 cs 4 vcc 8 out 7 gnd 6 zcd 5 c105 224/275v u203 fod817 1 2 3 4 d204 ll4148 24v/3a gnd c208 474/2012 d201 ffpf20up30dn r209 473/2012 fg lf101 45mh 1 3 2 4 c209 474/2012 r201 0.1/5w d106 rs1m c108 105/2102 d202 ffpf20up30dn c116 104/2012 zd103 24b 1w lf102 45mh 1 3 2 4 r211 203 d107 rs1m r125 430/3216 r126 430/3216 r206 133/2012 r108 203/3216 r127 203/3216 c113 104/2012 t rt1 5d-9 c114 33uf/50v rv1 10d471 t rt2 5d-9 c212 102/3216 c109 105/2102 q101 fcpf16n60 r216 163/2012 c213 102/3216 r109 100/3216 r110 4r7/3216 d102 ll4148
AN-9736 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/8/11 12 3.4. bill of materials item no. part reference value qty. description (manufacturer) 1 u101 fl6961 1 crm pfc controller (fairchild semiconductor) 2 u102 fl6300a 1 qr pwm controller (fairchild semiconductor) 3 q101 fcpf20n60 1 600v/20a mosfet (fairchild semiconductor) 4 q102 fqpf8n80 1 800v/8a mosfet (fairchild semiconductor) 5 d201,d202 ffpf20up30dn 2 ultra-fast recovery power rectifier (fairchild semiconductor t) 6 d103 egp30j 1 600v/3a ultra-fast recovery diode (fairchild semiconductor) 7 d104,d106,d107,d108 rs1m 4 1000v/1a ultra-fast recovery diode (fairchild semiconductor) 8 d101 kbl06 1 bridge diode (fairchild product) 9 q201 mmbt2222a 1 general-purpose trans istor (fairchild semiconductor) 10 u202 lm2904 1 dual op amp (fairchild semiconductor) 11 u203 fod817 1 opto-coupler (fairchild semiconductor) 12 u201 ka431s 1 shunt rregulator (fairchild semiconductor) 13 zd103 24b 1w 1 zener diode (fairchild semiconductor) 14 zd201 15b 1 zener diode (fairchild semiconductor) 15 d102,d105,d203,d204, d205 ll4148 5 general-purpose diode (fairchild semiconductor) 16 c101 684/275v 1 x ? capacitor 17 c102 334/275v 1 x ? capacitor 18 c105 224/275v 1 x ? capacitor 19 c103,c104 472(y) 2 y ? capacitor 20 c211 222(y) 1 y ? capacitor 21 c106,c114,c206 33f/50v 3 electrolytic capacitor, 105c 22 c107,c113,c116,c207 104/2012 4 smd capacitor 2012 23 c108,c109, c210 105/2102 3 smd capacitor 2012 24 c110 68f/450v 1 electrolytic capacitor, 105c 25 c111 222 1kv 1 ceramic-capacitor 26 c112,c117 200/2012 2 smd capacitor 2012 27 c201,c202,c203,c204, c205 1000f/35v 5 electrolytic capacitor, 105c 28 c208,c209 474/2012 2 smd capacitor 2012 29 c212,c213 102/3216 2 smd capacitor 3216 30 f101 220v/2a 1 fuse 31 l101 ei2820 1 pfc inductor (v10p), 450h 32 l201 10h 1 stick inductor 33 lf101,lf102 45mh 2 line filter 34 r101,r102,r103,r104 104/3216 4 smd resistor 3216 35 r128 393/3216 1 smd resistor 3216 36 r105,r106,r107,r131 433/3216 4 smd resistor 3216 37 r108,r124,r127 203/3216 3 smd resistor 3216 38 r109,r118 100/3216 2 smd resistor 3216 39 r110,r119 4r7/3216 2 smd resistor 3216 40 r111,r122 0r2 2w 2 metal film resistor 2w 41 r112,r113,r114 394/3216 3 smd resistor 3216 42 r115 682/3216 1 smd resistor 3216 43 r213,r214 153/3216 2 smd resistor 3216 44 r116,r117 150k ? /2w 2 metal oxide film resistor 2w
AN-9736 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/8/11 13 bill of materials (continued) item no. part reference value qty. description (manufacturer) 45 r120 151/3216 1 smd resistor 3216 46 r123 224/3216 1 smd resistor 3216 47 r125,r126 430/3216 2 smd resistor 3216 48 r129,r130 103/3216 2 smd resistor 3216 49 r201 0.1/5w 1 mpr resistor 5w 50 r202 152/2012 1 smd resistor 2012 51 r203 513/2012 1 smd resistor 2012 52 r204 753/2012 1 smd resistor 2012 53 r205 392/2012 1 smd resistor 2012 54 r206 133/2012 1 smd resistor 2012 55 r207,r209 473/2012 2 smd resistor 2012 56 r208 302/2012 1 smd resistor 2012 57 r212 432/2012 1 smd resistor 2012 58 r210 153/2012 1 smd resistor 2012 59 r216 223/2012 1 smd resistor 2012 60 r211 20k ? 1 variable resistor 61 rt1,rt2 5d-9 2 ntc 62 t2 eer3124 1 qr transformer(v10p), 500h 63 rv1 10d471 1 varistor 4.0 related datasheets fl6961 - single stage flyback and boundary mode pfc controller for lighting ? fl6300a -quasi-resonant current mode pwm controller for lighting application note - an-6300 fan6300/a/h - highly integr ated quasi-resonant pwm controller application note - an-6961- critical conduction mode pfc controller disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described he rein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as criti cal components in life support devices or systems without the express written approval of the preside nt of fairchild semiconductor corporation. as used herein: 1. life support devices or system s are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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